Problem Statement 1:
IC’s today have more than 1000 pins available on a single chip, each of them having various properties and capabilities as per the design requirements. Hence, a large amount of time is devoted in designing and testing these I/O cells. In order to minimize the design time and design complexity, standard specifications for I/O cells are identified and are designed to meet these specifications. Such I/O cells are typically called as “Standard I/O Cell” because of its common interface implementation and regular structure. Standard I/O cells are similar to Logical Standard Cells, and are designed as similar to standard cell design, but more consideration is given to their driving capability and their interfaces.
The basic building blocks of the I/O cells are the ESD protection network, pull up and pull down network, driver circuit, and level shifter circuit, PLL and storage element.
The purpose of this assignment is to design, analyze and implement I/O cells as standard cells for VLSI Design. Part-A of the assignment focuses on literature review of I/O cells and discussion on I/O cell designs, Part-B of the assignment focuses on design and schematic capture of I/O cell and Part-C of assignment focuses on verification of I/O cell design.
Problem Statement 2:
Design of 4x4 SRAM in 180 nm Technologu
Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in a particular system depends on the type of the application, but, in general, the number of transistor for the information (data) storage function is much larger than the number of transistors used for logic operations and other purpose. The ever increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, towards higher data storage densities. On-chip memory array have become widely used subsystems in many VLSI circuits, and commercially available single –chip read/write memory capacity has been reached in gigabits range.
The purpose of this assignment is to help the student’s design of full custom memory with 6T CMOS cell configuration. Use the knowledge acquired from theory and practical class and work with CAD tools to model the design efficiently. The most important parts in the memory design are peripheral circuits which are connected to and around the 6T SRAM cell.Design and draw schematic and layout diagram of peripheral circuits like Sense amplifier, write circuit and decoder circuits.
Design a SRAM memory circuits should have all the following specifications.
Problem Statement 3:
Design and development of an automatic Power Supply Controller
Nowadays automatic controllers are becoming more popular due to its Reconfigurability, power saving options, less external passive components, less sensitive to temperature variations and its high efficiency. Development of commercial electronic products requires development of prototypes on embedded controllers. In this part of the assignment students have to develop an FPGA based automatic power supply control system.
Students are required to develop an automatic controller for controlling the complete power supply in a department consisting of seven members. The controller should be capable to control the working of light, fan, computers and all other electronic equipments.
Problem Statement 4:
Design and development of Tank Water Level Control System
In this part of the assignment, the students need to identify the resourceful synthesis methodologies and techniques for implementing Tank Water Level Control System. Using relevant scripts the Verilog model should be synthesized to meet the targeted specifications. Static Timing Analysis should be carried out on the netlist to prove that it is timing clean. The HDL should be simulated in an industry standard simulator and then synthesized to meet the following specifications.
Problem Statement 2:
Design of 4x4 SRAM in 180 nm Technologu
Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in a particular system depends on the type of the application, but, in general, the number of transistor for the information (data) storage function is much larger than the number of transistors used for logic operations and other purpose. The ever increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, towards higher data storage densities. On-chip memory array have become widely used subsystems in many VLSI circuits, and commercially available single –chip read/write memory capacity has been reached in gigabits range.
The purpose of this assignment is to help the student’s design of full custom memory with 6T CMOS cell configuration. Use the knowledge acquired from theory and practical class and work with CAD tools to model the design efficiently. The most important parts in the memory design are peripheral circuits which are connected to and around the 6T SRAM cell.Design and draw schematic and layout diagram of peripheral circuits like Sense amplifier, write circuit and decoder circuits.
Design a SRAM memory circuits should have all the following specifications.
- Organization: 4X4-bit SRAM IC
- Storage Capacity: 16 bits
- SRAM implemented using the full CMOS 6T configuration
- Fabrication Technology: TSMC 0.18um
Design and development of an automatic Power Supply Controller
Nowadays automatic controllers are becoming more popular due to its Reconfigurability, power saving options, less external passive components, less sensitive to temperature variations and its high efficiency. Development of commercial electronic products requires development of prototypes on embedded controllers. In this part of the assignment students have to develop an FPGA based automatic power supply control system.
Students are required to develop an automatic controller for controlling the complete power supply in a department consisting of seven members. The controller should be capable to control the working of light, fan, computers and all other electronic equipments.
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| ARCHITECTURE OF THE CONTROLLER |
Problem Statement 4:
Design and development of Tank Water Level Control System
In this part of the assignment, the students need to identify the resourceful synthesis methodologies and techniques for implementing Tank Water Level Control System. Using relevant scripts the Verilog model should be synthesized to meet the targeted specifications. Static Timing Analysis should be carried out on the netlist to prove that it is timing clean. The HDL should be simulated in an industry standard simulator and then synthesized to meet the following specifications.
Specification:
- Frequency : Min 200 MHz
- Leakage Power: 10 uw
- The 65nm multi VTH, multi VDD, TSMC process should be used for synthesis
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| Relation between level sensor inputs and outputs to the pump |
Low Power Implementation and DFT for Tank Water Level Control System
In this part of the work the student needs to identify the best possible DFT methodology with also focus on low power for the Tank Water Level Control System designed previously. The design should be able to meet the following specifications
- Fault Coverage : 98.5%
- Dynamic Power : <10 uw
Problem Statement 5:
ASIC Verification of Intelligent Traffic Light Control System
The Intelligent Traffic Light Control System has one FSM which acts as the heart of the entire system. The control system has only certain fixed conditions to fulfill in order to control the traffic lights that control traffic flow. Figure shows an interchange junction of four roads. Traffic crossing the interchange junction needs to be regulated by a traffic light system in order to enable a smooth and safe interchange crossing for motorized
vehicles. Assume that a design is needed to control the traffic light system. The inputs timerGreen, timerYellow, and timerRed are assumed to be generated from an external timer module that allows the traffic light controller to “know” that the allocated time period for the traffic lights at GREEN, YELLOW, or RED is exhausted and the traffic lights are to switch colors. It is also assumed that this timer module takes the inputs from the eight sensors to allow it to automatically determine if a certain traffic light should be at GREEN, YELLOW, or RED for a longer or shorter period of time before switching to another color.
ASIC Verification of Intelligent Traffic Light Control System
The Intelligent Traffic Light Control System has one FSM which acts as the heart of the entire system. The control system has only certain fixed conditions to fulfill in order to control the traffic lights that control traffic flow. Figure shows an interchange junction of four roads. Traffic crossing the interchange junction needs to be regulated by a traffic light system in order to enable a smooth and safe interchange crossing for motorized
vehicles. Assume that a design is needed to control the traffic light system. The inputs timerGreen, timerYellow, and timerRed are assumed to be generated from an external timer module that allows the traffic light controller to “know” that the allocated time period for the traffic lights at GREEN, YELLOW, or RED is exhausted and the traffic lights are to switch colors. It is also assumed that this timer module takes the inputs from the eight sensors to allow it to automatically determine if a certain traffic light should be at GREEN, YELLOW, or RED for a longer or shorter period of time before switching to another color.
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| Intelligent Traffic Light Control System |
Specification:
- Frequency : Min 800 MHz
- Leakage Power < 15 uw
- The 65nm multi VTH, multi VDD, TSMC process should be used for synthesis
In this part of the work, the students need to identify the resourceful verification methodologies and techniques for verifying Traffic Light control system. Then the student needs to identify the best possible constraint random verification technique with focus on efficient code coverage for the Traffic Light Control System verified.
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